Evaluating Multiplier-Less CNNs in RISC-V Architecture

EasyChair Preprint 15741

Abstract

In recent years Convolutional Neural Network (CNN) emerged as Machine Learning (ML) became a popular approach to solve problems in distributed area computations such as mobile devices and Internet of Things (IoT). It is well known that local computation at edge devices is preferable over transmitting a huge amount of data to run ML algorithms at a central node. In this sense, RISC-V has the research community’s attention as a flexible architecture and royalty-free alternative for embedded processors and IoT devices. Although the latest research on RISC-V and CNNs has been instruction set architecture (ISA) customization to speed up the convolution process, this work investigates the impact on inference execution time when replacing multiplication instructions by shift in multiply and accumulate (MAC) operations. Compared to slow multi-cycle multiplication instructions, our experiments showed inference throughput speedup ranging from 1.45x to 1.95x with negligible impact on memory footprint and employing only the base integer RISC-V ISA (RV32I).

Keyphrases: Convolution Neural Networks, MAC operation, Quantization, RISC-V, power of two, shift

@booklet{EasyChair:15741,
  author    = {Bruno Henrique Spies and Mathias Cirolini Michelotti and Leonardo Londero de Oliveira and Everton Alceu Carara},
  title     = {Evaluating Multiplier-Less CNNs in RISC-V Architecture},
  howpublished = {EasyChair Preprint 15741},
  year      = {EasyChair, 2025}}