The iMACAW aims at providing a forum to discuss In-Memory-Computing as an alternative architecture and its applications. We take a cross-technology approach covering works that use SRAM, DRAM, FLASH, RRAM, PCM, MRAM, and FeFET as their memory technology. The workshop features renowned speakers from academia and industry, plus a limited selection of best submissions.

Submission Guidelines

Please submit an extended abstract up to 2 pages using the IEEE conference format to be considered for presenting your work as an oral presentation and interact with workshop attendees (alongside coffee breaks). The submission should include authors name, organization, and email address.IEEE conference format: https://www.ieee.org/conferences/publishing/templates.html 

Areas of Interest

• In-memory computing devices, including but not limited to, MRAM, RRAM, PCM, FeFET, 2D, etc.
• In-memory computing circuit designs based on CMOS or post-CMOS technologies
• In-memory computing architecture, compiler
• In-memory computing applications
• In-memory computing software-hardware co-design

Organizing Committee

• Nima Taherinejad (Heidelberg University, Heidelberg, Germany): nima@uni-heidelberg.de
• Deliang Fan (Arizona State University, Arizona, USA): dfan@asu.edu
• Wantong Li (University of California, Riverside, California, USA): wantong.li@ucr.edu

Publication

DAC will not produce proceedings for workshops, however, the workshop organizers collect the camera-ready submissions and publish them on the workshop website. Additionally, the authors have the opportunity to submit an extension of their work to a special issue associated with the workshop (the specific journal and submission details will be announced later).

Venue

The workshop will be held on Sunday, June 22, 2025, Co-Located with DAC 2025, at Moscone Center West in San Francisco, CA.