DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well as general purpose languages such as C, C++, Python, PERL and Tcl. Tools and methodologies include the use of artificial intelligence, machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP-based SoC design methods, reference flows and Mixed Signal design and verification.

Submission Guidelines

All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome.

• Short papers describing the application of languages, tools, flows, methodologies and their relevant AI approach for the design and verification of electronic systems and integrated circuits.
• Draft version of the slides describing the application of languages, tools, flows, methodologies and their relevant AI approach for the design and verification of electronic systems and integrated circuits.

Committees

Program Committee

• Takahide Yoshikawa (Fujitsu)
• Hiroshi Hosokawa (Canon)
• Takahisa Hashimoto (SONY)
• Kazutoshi Wakabayashi (Tokyo University)
• Yukihiro Sasagawa (Socionext)

Organizing Committee

• Genichi Tanaka (Advantest)
• Yoshinari Ojima (Toshiba)
• Motoki Higashida (Verification Technology)
• Tetsuya Asano (Renesas Electronics)
• Takehiro Suzuki (CM Engineering)
• Akio Mitsuhashi (EE Tech Focus)

Venue

The conference will be held in Pacifico Yokohama North.

Contact

All questions about submissions should be emailed to akio_mitsuhashi@eetechfocus.com