ATS 2026: 2026 35th Asian Test Symposium Hotel Nikko Kaohsiung Kaohsiung, Taiwan, November 18-20, 2026 |
| Conference website | https://www.ats2026.tw/ |
| Submission link | https://easychair.org/conferences/?conf=ats2026 |
| Submission deadline | May 24, 2026 |
Submission Guidelines
The ATS 2026 Organizing Committee invites original, unpublished paper submissions on the topics listed below.
Submission Guidelines
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Format: Regular paper submissions must be made electronically in PDF format only.
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Page Limit: Manuscripts must not exceed 6 pages in IEEE 2-column format (A4 size, including abstract, figures, tables, and bibliography).
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Template: Please adhere to the standard IEEE conference templates.
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Originality: Submissions must be original and should not be under consideration for publication elsewhere.
Author Requirements
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Presentation: A submission will be considered evidence that, upon acceptance, at least one author will attend the conference to make the presentation.
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Registration: At least one full (non-student) registration to the conference is required for each accepted paper.
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Final Manuscript: Authors of accepted papers are responsible for preparing the final camera-ready manuscripts in time to be included in the electronic proceedings.
Important Dates
- Submission deadline: May 24, 2026
- Notification of acceptance: Aug. 31, 2026
- Camera ready manuscript: Sep. 30, 2026
List of Topics
The conference covers all aspects of testing and reliability. Topics of interest include, but are not limited to:
- AI test and Test for AI
- Analog/Mixed-Signal Test
- ATE Design
- Automatic Test Pattern Generation (ATPG)
- Autonomous Testing
- Board-Level Testing and Diagnosis
- Boundary Scan Test
- Built-In Self-Test (BIST)
- CPU/GPU Test
- Connectivity Testing
- Defect-Based Test
- Delay and Performance Test
- Dependability and Functional Safety
- Design Verification, Validation, and Debug
- Design for Testability (DFT)
- Diagnosis and Silicon Debug
- Fault Diagnosis and Failure Analysis
- Fault Modeling and Simulation
- Fault Tolerance
- Hardware Oriented Security and Trust
- High-Speed I/O Test
- Heterogeneous Testing
- Low-Power IC Test
- Machine Learning in Test
- Memory Test, Diagnosis, and Repair
- Multi-/Many-core Processor Test
- Online Test
- On-Chip Measurement
- Power/Thermal/Reliability Issues in Test
- Reconfigurable System Test
- Reliability and Testing for Emerging/Approximate/Quantum Computing
- RF Test
- Safety and Test for Automotive ICs
- Self-Repair
- SiP, Chiplet, 2.5D and 3D IC Test
- Software Test and Reliability
- Standards in Test
- System-on-Chip Test
- Test Compression
- Test Economics
- Test Quality
- Test Synthesis
- Test for Biomedical Circuits and Systems
- Test for MEMS and Microfluidic Systems
- Test for Nanoscale Devices and Emerging Technologies
- Test for Reversible and Quantum Circuits
- Test for Sensors and IoT
- Yield Analysis, Learning, and Enhancement
Committee
Organizing committee
- General Chair: Jing-Jia Liou (National Tsing Hua University, Taiwan)
- Program Chair: Tong-Yu Hsieh (National Sun Yat-sen University, Taiwan)
- Finance Chair: Jiun-Lang Huang (National Taiwan University, Taiwan)
- Local Arrangement Chair: Ching-Hwa Cheng (Feng-Chia University, Taiwan)
- Registration Chair: Hao-Chiao Hong (National Yang Ming Chiao Tung University, Taiwan)
- Publicity Chair: Jin-Fu Li (National Central University, Taiwan)
- Publication Chair: Sying-Jyan Wang (National Chung Hsing University, Taiwan)
- Tutorial Chair: Charles H.-P. Wen (National Yang Ming Chiao Tung University, Taiwan)
- North American Liaison: Krishnendu Chakrabarty (Arizona State University, United States of America)
- European Liaison: Ilia Polian (University of Stuttgart, Germany)
Publication
Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore's scope and quality requirements.
Venue
Hotel Nikko Kaohsiung, Taiwan
Contact
For questions regarding submissions, please contact Mr. Yung-Ming Chiu at pobsadue@poetry-life.com